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1 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram preliminary some of contents are subject to change without notice. description m2s28d20atp is a 4-bank x 8388608-word x 4-bit, m2s28d30atp is a 4-bank x 4194304-word x 8-bit, m2s28d40atp is a 4-bank x 2097152-word x 16-bit, double data rate synchronous dram, with sstl_2 interface. all control and address signals are referenced to the rising edge of clk. input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of clk. the m2s28d20/30/40atp achieves very high speed data rate up to 133mhz, and are suitable for main memory in computer systems. features - vdd=vddq=2.5v +0.2v - double data rate architecture; two data transfers per clock cycle - bidirectional, data strobe (dqs) is transmitted/received with data - differential clock inputs (clk and /clk) - dll aligns dq and dqs transitions with clk transitions edges of dqs - commands entered on each positive clk edge; - data and data mask referenced to both edges of dqs - 4 bank operation controlled by ba0, ba1 (bank address) - /cas latency- 2.0/2.5 (programmable) - burst length- 2/4/8 (programmable) - burst type- sequential / interleave (programmable) - auto precharge / all bank precharge controlled by a10 - 4096 refresh cycles /64ms (4 banks concurrent refresh) - auto refresh and self refresh - row address a0-11 / column address a0-9,11(x4)/ a0-9(x8)/ a0-8(x16) - sstl_2 interface - 400-mil, 66-pin thin small outline package (tsop ii) - fet switch control(/qfc) for x4/ x8 - jedec standard
2 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram clk,/clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dq0-7 : data i/o dqs : data strobe dm : write mask /qfc : fet switch control for x4/x8 vref : reference voltage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 vss 66pin tsop(ii) 400mil width x 875mil length 0.65mm lead pitch row a0-11 column a0-9,11(x4) a0-9 (x8) a0-8 (x16) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nu,/qfc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 vss a0-11 : address input ba0,1 : bank address input vdd : power supply vddq : power supply for output vss : ground vssq : ground for output vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc nc a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nu,/qfc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd pin configuration(top view) x8 x16 x4
3 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram type designation code this rule is applied to only synchronous dram family. mitsubishi main designation speed grade 10: 125mhz@cl=2.5,100mhz@cl=2.0 75: 133mhz@cl=2.5,100mhz@cl=2.0 package type tp: tsop(ii) process generation function reserved for future use organization 2 n 2: x4, 3: x8, 4: x16 ddr synchronous dram density 28: 128m bits interface v:lvttl, s:sstl_3, _2 memory style (dram) m 2 s 28 d 3 0 a tp -75 block diagram /cs /ras /cas /we udm, ldm memory array bank #0 dq0 - 15 i/o buffer memory array bank #1 memory array bank #2 memory array bank #3 mode register control circuitry address buffer a0-11 ba0,1 clock buffer clk, /clk cke control signal buffer /qfc for x4/x8 qfc&qs buffer udqs,ldqs dll
4 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram pin function clk, /clk input clock: clk and /clk are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of /clk. output (read) data is referenced to the crossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-11. the column address is specified by a0-9,11(x4), a0-9(x8) and a0-8(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input dq0-15(x16), dq0-7(x8), dq0-3(x4), input / output dqs vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge- aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs correspond to the data on dq8-dq15 symbol type description /qfc output fet control: optional. output during every read and write access. can be used to control isolation switches on modules. open drain output. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0- dq7; udm corresponds to the data on dq8-dq15. input / output vref input sstl_2 reference voltage.
5 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram basic functions the m2s28d20/30/40atp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands /clk activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto- precharge, reada) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea) . precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically.
6 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11 deselect desel hxhxxxxxx no operation nop hxlhhhxxx row address entry & bank activate act hhllhhvvv single bank precharge pre hhllhlvlx precharge all banks prea h h l l h l h x column address entry & write write hhlhllvlv column address entry & write with auto-precharge writea h h l h l l v h v column address entry & read read hhl hl hvl v column address entry & read with auto-precharge reada hhlhl hvhv auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx lhhxxxxxx lhlhhhxxx burst terminate term h h l h h l x x x mode register set mrs hhllllllv x note 1 note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0=1 , ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a11 provide the 2 2. op-code to be written to the selected mode register.
7 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram function truth table current state /cs /ras /cas /we address command action notes idle h x x x x desel nop lh hhx nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop 4 ll lhx refa auto-refresh 5 ll l l op-code, mode- add mrs mode register set 5 row active h x x x x desel nop lh hhx nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto- precharge 3 l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll l l op-code, mode- add mrs illegal read(auto- precharge disabled)
8 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge 3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge 3 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal write(auto- precharge disabled) read with auto-precharge write with auto-precharge
9 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea nop (idle after trp) 4 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal ll l l op-code, mode- add mrs illegal row activating write re- covering pre- charging
10 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram function truth table (continued) abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. current state /cs /ras /cas /we address command action notes refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trsc) l h h h x nop nop (row active after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal ll l l op-code, mode- add mrs illegal mode register setting
11 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously. . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we address action notes h x xxxx xinvalid 1 l h hxxx xexit self-refresh (idle after trc) 1 l h l h h h x exit self-refresh (idle after trc) 1 l h l h h l x illegal 1 l h lhlxxillegal 1 l h l l x x x illegal 1 l l xxxx xnop (maintain self-refresh) 1 h x xxxx xinvalid l h xxxx xexit power down to idle l l xxxx xnop (maintain self-refresh) h h xxxx xrefer to function truth table 2 h l l l l h x enter self-refresh 2 h l hxxx xenter power down 2 h l l h h h x enter power down 2 h l l h h l x illegal 2 h l lhlxxillegal 2 h l l l x x x illegal 2 l x xxxx xrefer to current state =power down2 h h xxxx xrefer to function truth table h l xxxx xbegin clk suspend at next cycle 3 l h xxxx xexit clk suspend at next cycle 3 l l xxxx xmaintain clk suspend any state other than listed above self- refreshing power down all banks idle
12 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram simplified state diagram row active idle pre charge power down read reada write writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term
13 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or multifunctioning. 1. apply vdd before or the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable condition for 200us after stable power and clk, apply nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs 6. issue mrs for the mode register and to reset the dll 7. issue 2 or more auto refresh commands 8. maintain stable condition for 200 cycle after these sequence, the ddr sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from a mrs command, the ddr sdram is ready for new command. /cs /ras /cas /we a11-a0 /clk v clk ba0 ba1 r: reserved for future use 0no 1yes dll reset 0 sequential 1 interleaved burst type bt=0 bt=1 000 r r 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r 111 r r bl burst length /cas latency 000 r 001 r 010 2 011 r 100 r 101 r 110 2.5 111 r cl latency mode ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 00000dr0 bt ltmode bl
14 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram extended mode register dll disable / enable mode can be programmed by setting the extended mode register (emrs). the extended mode register stores these data until the next emrs command, which may be issued when all banks are in idle state. after trsc from a emrs command, the ddr sdram is ready for new command. /cs /ras /cas /we a11-a0 v ba0 ba1 /clk clk ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 00000000000 qfc ds dd 0disable 1enable qfc 0normal 1weak drive strength 0 dll enable 1 dll disable dll disable
15 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 000 001 010 011 100 101 110 111 -00 -01 -10 -11 --0 0123456701234567 1234567010325476 2345670123016745 3456701232107654 4567012345670123 5670123454761032 6701234567452301 701 2 012 3 123 0 230 1 30 01 7654 0123 1032 2301 32 01 --1 12 10 3456 3210 10 10 8 4 2 command address dq yy read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk
16 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram absolute maximum ratings dc operating conditions (ta=0 ~ 70 o c, unless otherwise noted) capacitance (ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, unless otherwise noted) min. max. ci(a) input capacitance, address pin 2.0 3.0 pf 11 ci(c) input capacitance, control pin vi=1.25v 2.0 3.0 pf 11 ci(k) input capacitance, clk pin f=100mhz 2.0 3.0 0.25 pf 11 ci/o i/o capacitance, i/o, dqs, dm pin vi=25mvrms 4.0 5.0 pf 11 co(qf) output capacitance, /qfc 2.0 3.0 pf 11 notes limits symbol parameter test condition unit delta cap.(max.) 0.50 0.50 min. t yp .max. vdd su pp l y volta g e 2.3 2.5 2.7 v v ddq su pp l y volta g e for o ut p ut 2.3 2.5 2.7 v vref in p ut reference v olta g e 0.49*v ddq 0.50*v ddq 0.51*v ddq v 5 vih(dc) hi g h-level in p ut v olta g e v ref + 0.18 v ddq +0.3 v vil(dc) low-level in p ut v olta g e -0.3 v ref - 0.18 v vin(dc) in p ut v olta g e level, clk and /clk -0.3 v ddq + 0.3 v vid(dc) in p ut d ifferential v olta g e, clk and /clk 0.36 v ddq + 0.6 v 7 v t t i /o t e r m in a tio n v o lta g e v ref - 0.04 v ref + 0.04 v 6 notes limits s y mbol p arameter u nit symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 3.7 v vddq supply voltage for output with respect to vssq -0.5 ~ 3.7 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vssq -0.5 ~ vddq+0.5 v io output current 50 ma pd power dissipation ta = 25 o c 1000 mw topr operating temperature 0 ~ 70 o c tstg storage temperature -65 ~ 150 o c
17 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram -75 -10 x4 105 95 x8 110 105 x16 120 115 x4 110 100 x8 115 110 x16 135 130 x4 60 55 x8 65 60 x16 75 70 x4 150 140 x8 170 160 x16 210 200 x4 145 135 x8 165 155 x16 200 180 idd5 auto refresh current: t rc = t rfc (min) x4/x8/x16 190 180 idd6 self refresh current: cke < 0.2v x4/x8/x16 3 3 9 x4/x8/x16 40 40 limits(max.) ma symbol organization parameter/test conditions idd4r operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle;cl=2.5; t ck = t ck min; iout = 0 ma precharge power-down standby current: all banks idle; power- down mode; cke < vil (max); t ck = t ck min x4/x8/x16 idd2p idd2n idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs changing once per clock cycle idd4w operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2.5; t ck = t ck min;dq, dm and dqs inputs changing twice per clock cycle idd3p active power-down standby current: one bank active; power- down mode; cke < vil (max); t ck = t ck min active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n x4/x8/x16 operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 idd1 operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; iout= 0ma; address and control inputs changing once per clock cycle 40 40 unit notes 20 20 average supply current from vdd (ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, output open, unless otherwise noted) min. max. vih(ac) hi g h-level in p ut v olta g e (ac ) vref + 0.35 vil(ac) low-level in p ut v olta g e (ac ) vref - 0.35 vid(ac) in p ut differential volta g e, clk and /clk 0.7 vddq + 0.6 7 vix(ac) in p ut c rossin g p o in t v o lta g e, clk and /clk 0.5*vddq - 0.2 0.5*vddq + 0.2 8 io z o ff- state o ut p ut c urrent /q floatin g vo=0~vddq -5 5 m a ii in p ut current / vin=0 ~ vddq -2 2 m a io h o ut p ut hi g h current (vo ut = 1.95 v) -16.8 io l o ut p ut hi g h current (vo ut = 0.35 v) 16.8 ma ma notes limits s y m b o l p a r a m e te r / t e s t c o n d itio n s u n it v v v v
18 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram ac timing requirements (ta=0 ~ 70 o c, vdd = vddq = 2.5v +0.2v, vss = vssq = 0v, unless otherwise noted) min. max min. max tac dq output valid data delay time from clk//clk -0.75 0.75 -0.8 0.8 ns tdqsck dq output valid data delay time from clk//clk -0.75 0.75 -0.8 0.8 ns tch clk high level width 0.45 0.55 0.45 0.55 ns tcl clk low level width 0.45 0.55 0.45 0.55 ns 7.515815ns 10 15 10 15 ns tdh input setup time (dq,dm) 0.5 0.6 ns tds input hold time(dq,dm) 0.5 0.6 ns tdipw dq and dm input pulse width (for each input) 1.75 2 ns thz data-out-high impedance time from clk//clk -0.75 0.75 -0.8 0.8 ns 14 tlz data-out-low impedance time from clk//clk -0.75 0.75 -0.8 0.8 ns 14 tdqsq dq valid data delay time from dqs -0.5 0.5 -0.6 0.6 ns thp clock half period tclmin or tchmin tclmin or tchmin ns tqh output dqs valid window thp-0.75 thp-1.0 ns tdqss write command to first dqs latching transition 0.75 1.25 0.75 1.25 tck tdqsh dqs input high level width 0.35 0.35 tck tdqsl dqs input low level width 0.35 0.35 tck tdss dqs falling edge to clk setup time 0.2 0.2 tck tdsh dq s falling edge hold time from c lk 0.2 0.2 tc k tmrd mode register set command cycle time 15 15 ns twpres write preamble setup time 0 0 ns 16 twpst write postamble 0.4 0.6 0.4 0.6 tck 15 twpre write preamble 0.25 0.25 tck tis input setup time (address and control) 0.9 1.2 ns 19 tih input hold time (address and control) 0.9 1.2 ns 19 trpst read postamble 0.4 0.6 0.4 0.6 tck trpre read preamble 0.9 1.1 0.9 1.1 tck tqpst /qfc postamble during reads 0.4 0.6 0.4 0.6 tck tqpre /qfc preamble during reads 0.9 1.1 0.9 1.1 tck tqck /qfc output access time from clk//clk, for write 4 4 ns tqoh /qfc output hold time for writes 1.25 2 1.25 2 ns -10 unit notes tck clk cycle time symbol ac characteristics parameter -75
19 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram ac timing requirements(continues) (ta=0 ~ 70 o c, vdd = vddq = 2.5v +0.2v, vss = vssq = 0v, unless otherwise noted) min. max min. max tras row active time 45 120,000 50 120,000 ns trc row cycle time(operation) 65 70 ns trfc auto ref. to active/auto ref. command period 75 80 ns trcd row to column delay 20 20 ns trp row precharge time 20 20 ns trrd act to act delay time 15 15 ns twr write recovery time 15 15 ns tdal auto precharge write recovery + precharge time 35 35 ns twtr internal write to read command delay 1 1 tck txsnr exit self ref. to non- read command 75 80 ns txsrd exit self ref. to -read command 200 200 tck txpnr exit power down to command 1 1 tck txprd exit power down to -read command 1 1 tck 18 trefi average periodic refresh interval 15.6 15.6 m s17 -10 unit notes symbol ac characteristics parameter -75 output load condition dq output timing measurement reference point v ref v ref dqs v out v ref 30pf 50 w v tt =v ref zo=50 w
20 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifications are tested after the device is properly initialized. 11. this parameter is sampled. vddq = 2.5v +0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25 o c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke < 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns.
21 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram /clk dqs tis tih vref clk valid data /qfc read operation tac tdqsck tcl tch tck tdqsq tqh trpre trpst dqs /qfc /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=max. tdss twpres twpst tqck tqoh(min) tqpre tqpst dqs /qfc /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=min. tdsh twpres twpst tqck tqoh(max) dq dq dq cmd & add.
22 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a11-0. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc,although the number of banks which are active concurrently is not limited. bank activate operational description the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. precharge bank activation and precharge all (bl=8, cl=2) a precharge command can be issued at bl/2 from a read command without data loss. precharge all command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 qa1 qa2 qa3 qa4 qa5 qa6 qa7 /clk clk
23 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl-1) consecutive data when the burst length is bl. the start address is specified by a11,a9-a0(x4)/a9-a0(x8)/a8-a0(x16), and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2 after reada. the next act command can be issued after (bl/2+trp) from the previous reada. read multi bank interleaving read (bl=8, cl=2) /clk command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length dqs qa0 clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8
24 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram trcd trp bl/2 bl/2 + trp read with auto-precharge (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 1 00 act xb xb 00 internal precharge start dqs /clk clk read auto-precharge timing (bl=8) command act read internal precharge start timing dq cl=2.5 bl/2 dq cl=2 qa0 /clk clk qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7
25 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram after trcd from the bank activation, a write command can be issued. 1st input data is set from the write command with data strobe input, following (bl-1) data are written into ram, when the burst length is bl. the start address is specified by a11,a9-a0(x4)/a9-a0(x8)/a8-a0(x16), and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last data to the pre command, the write recovery time (twrp) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next act command can be issued after tdal from the last input data cycle. write multi bank interleaving write (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd d trcd d pre xa 0 00 pre dqs write with auto-precharge (bl=8) command a0-9,11 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trc d da0 dqs /clk clk /clk clk da1 da2 da3 da4 da5 da6 da7 da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 tdal db4 db5 db6 db7 xa y xb xa ya yb xb
26 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram burst interruption [read interrupted by read] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1clk. read interrupted by read (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq yi read read read read yj yk yl 00 00 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk [read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
27 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
28 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram burst read operation can be interrupted by a burst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. [read interrupted by burst stop] read interrupted by term (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs
29 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram [read interrupted by write with term] read interrupted by term (bl=8) cl=2.5 command dq q0 q1 q2 q3 /clk clk read term dqs write d0 d1 d2 d3 d4 d5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7
30 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram burst write operation can be interrupted by write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [write interrupted by write] [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(twtr) is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". twtr is referenced from the first positive edge after the last data input. write interrupted by read (bl=8, cl=2.5) command a0-9,11 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr /clk clk write interrupted by write (bl=8) command a0-9,11 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk
31 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram burst write operation can be interrupted by precharge of the same or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. [write interrupted by precharge] write interrupted by precharge (bl=8, cl=2.5) command a0-9,11 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs dm twr /clk clk
32 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-9,11 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd mode register set, reset dll extended mode register set [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 128mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-11 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk cke initialize and mrs
33 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self- refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-11 ba0,1 txsnr self refresh exit /clk clk xy xy txsrd
34 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram [asynchronous self refresh] asynchronous self -refresh mode is entered by cke=l within 2 tclk after issuing a refa command (/cs=/ras=/cas=l,/we=h). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. asynchronous self-refresh /ras cke /cs /cas /we a0-11 ba0,1 txsnr self refresh exit max 2 tclk /clk clk
35 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram the purpose of clk suspend is power down. cke is synchronous input except during the self- refresh mode. a command at cycle is ignored. from cke=h to normal function, dll recovery time is not required in the condition of the stable clk operation during the power down mode. [power down] /clk clk power down by cke command pre cke command act cke standby power down nop nop valid nop nop valid active power down dm is defined as the data mask for writes. during writes,dm masks input data word by word. dm to write mask latency is 0. [dm control] dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 /clk clk q0 q1 q6 txpnr/txprd
36 mitsubishi electric jun,'00 preliminary mitsubishi lsis ddr sdram (rev.0.1) m2s28d20/ 30/ 40atp 128m double data rate synchronous dram keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page ( http://www.mitsubishichips.com) . when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.

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